Skip to content

CHAPTER 21

# Physical qubits, control, and hardware benchmarks

Learning goals. Compare physical encodings, identify control and scaling bottlenecks, and read performance metrics without treating qubit count as a complete measure.

## 21.1 An abstract qubit needs a physical boundary

A mathematical qubit is a two-dimensional system. A physical device usually has more states, interacts with an environment, and requires preparation, gates, measurement, and reset. An implementation chooses two usable states or an encoded subspace and controls unwanted couplings.

A complete processor includes the qubits, control electronics or optics, readout, classical processors, calibration, packaging, interconnects, and thermal or vacuum infrastructure. Counting only the quantum elements understates the engineering system.

Gate-based digital computation, analog quantum simulation, annealing, and photonic sampling devices expose different operations. Results from one model cannot be ranked directly against another without a common task. A large analog array is not automatically a universal circuit computer, although analog systems can be valuable scientific instruments.

## 21.2 Superconducting circuits

Superconducting qubits use nonlinear electrical circuits, commonly incorporating Josephson junctions. A transmon reduces sensitivity to charge noise while retaining enough anharmonicity to address two levels. Microwave pulses implement rotations; couplers or shared circuit elements produce entangling gates; resonators assist dispersive readout [54, 55].

Key concerns include energy relaxation, dephasing, leakage into higher levels, residual couplings, calibration drift, fabrication variation, and correlated disturbances. Cryogenic packaging and wiring must scale without introducing excessive heat or noise. Fast gates permit short code cycles but impose demanding classical decoding throughput.

A reported T1 or T2 is measured under a particular protocol. It does not directly predict all gate errors in a busy processor. Simultaneous-operation performance, leakage removal, readout, reset, and stability across many rounds matter for error correction.

## 21.3 Trapped ions

Ions encode qubits in internal atomic levels and are confined using electromagnetic fields. Laser or microwave interactions control individual qubits. Shared motional modes or controlled transport mediate entanglement; fluorescence provides state-dependent readout [56].

Identical atomic species offer reproducible transitions and long-lived internal states. Scaling requires control over motional heating, optical addressing, transport, mode crowding, crosstalk, and measurement while protecting other qubits. A quantum charge-coupled device architecture moves ions among zones for storage, gates, and readout.

The 2026 Helios paper describes a 98-qubit trapped-ion processor with all-to-all connectivity [59]. That connectivity is an architectural capability, not a statement that all pairs can perform independent gates simultaneously at zero transport or scheduling cost. The publication should be consulted for the exact benchmark circuit, fidelities, and timing.

## 21.4 Neutral atoms

Optical tweezers trap individual neutral atoms. Hyperfine, nuclear-spin, or other internal levels can encode qubits; interactions involving excited Rydberg states can produce entangling gates. Arrays may be rearranged, giving connectivity options different from fixed nearest-neighbor chips [57].

Atom loss, loading, transport, laser stability, Rydberg-state lifetime, crosstalk, and mid-circuit measurement are important. An array can trap many coherent atoms before demonstrating universal gates and error-corrected operations across all of them. Those are distinct milestones.

Bluvstein and collaborators’ work in a 2026 Nature issue used arrays of up to 448 atoms to investigate repeated correction, logical operations, and qubit reuse [49]. Its online publication preceded its issue date. Chapter 24 separates the demonstrated circuit scope from the larger architecture it motivates.

## 21.5 Photonics

Photonic qubits can use polarization, paths, time bins, or other optical degrees of freedom. Photons are natural communication carriers. Linear optics, interference, detection, ancillary photons, feed-forward, nonlinearities, and encoded resource states enable different computational architectures.

The principal challenge is often loss: source efficiency, coupling, propagation, switching, and detection all contribute. Indistinguishability and phase stability are also essential. A probabilistic entangling primitive may require multiplexing or a larger resource-state architecture to achieve useful logical throughput.

Modular photonic experiments study how components and networks can be assembled into larger systems [60]. A component crossing one modeled threshold is not the same as a complete fault-tolerant processor crossing all required thresholds simultaneously.

## 21.6 Semiconductor spins and other approaches

Electron or nuclear spins in semiconductor devices can use electrically controlled confinement, exchange interactions, and spin-selective readout. Their small physical footprint and relation to semiconductor manufacturing are attractive. Uniformity, charge noise, addressability, valley or orbital states, cryogenic control, and interconnects remain practical issues [58].

Defect centers combine localized spin memories with optical interfaces and are useful in networking and sensing. Bosonic encodings use oscillator states rather than a single two-level element. Topological approaches seek protection from nonlocal degrees of freedom, but demonstrating a particular parity signal is not by itself a demonstration of protected non-Abelian logical computation.

A 2025 Microsoft-associated paper reported interferometric parity measurement in hybrid devices [61]. Interpretation and diagnostic robustness have been disputed in subsequent research [62]. This book does not treat a company announcement or a candidate signature as settled evidence of a scalable topological computer.

## 21.7 Compare bottlenecks, not a universal winner

Platform | Typical information carrier | Important system questions
--- | --- | ---
Superconducting | Engineered circuit levels | Coherence, leakage, fabrication, wiring, fast feedback
Trapped ion | Internal atomic levels | Motion, transport, addressing, parallelism
Neutral atom | Trapped-atom internal levels | Loss, rearrangement, entangling control, reuse
Photonic | Optical modes or encoded states | Loss, sources, detectors, switching, feed-forward
Semiconductor spin | Confined electronic or nuclear spin | Uniformity, noise, control integration, connectivity
Bosonic / hybrid | Encoded oscillator or coupled degrees | Encoding-specific errors, control, ancillas, readout

These are representative concerns, not fixed rankings. Different platforms can be suitable for different workloads, and improvements in one component may shift the dominant bottleneck elsewhere.

## 21.8 What a benchmark measures

Gate fidelity compares a realized operation with a target according to a defined averaging convention. It is not the probability every gate is independently perfect. Randomized benchmarking fits decay under random gate sequences to infer parameters under assumptions about errors and SPAM. Process tomography reconstructs a channel with greater measurement cost and model sensitivity. Cross-entropy benchmarking and related sampling metrics target particular distributions and depend on calibration and theoretical assumptions.

Quantum volume, circuit-layer metrics, algorithmic benchmarks, and logical-error rates summarize different tasks. A number without the circuit family, statistical uncertainty, acceptance policy, and runtime definition is incomplete. Error bars should describe how uncertainty was estimated; repeated calibration may reveal drift larger than simple shot uncertainty.

A practical comparison asks for the same task, target accuracy, success probability, total time, and relevant classical baseline. “Advantage” can mean a sampling benchmark, a scientific computation, or economically useful performance. The word should be qualified.

## 21.9 Exercises

21.1. A device traps 6,000 atoms but demonstrates entangling gates on a subset. What can its atom count establish?

Show solution / guidance

It establishes a trapping-scale milestone under the reported conditions. It does not alone establish 6,000 universally controllable or logical qubits.

21.2. Why is a long idle coherence time insufficient to predict logical performance?

Show solution / guidance

Logical operation includes gates, readout, reset, leakage management, crosstalk, and decoding. Their errors and correlations may dominate idle decoherence.

21.3. Does all-to-all connectivity mean constant-depth arbitrary all-pairs computation?

Show solution / guidance

No. Shared resources, transport, addressing, and gate scheduling can constrain simultaneous operations.

21.4. Why can a photonic design with excellent gate components still have poor end-to-end success?

Show solution / guidance

Efficiencies multiply across sources, coupling, propagation, switching, and detection. Loss and probabilistic preparation can dominate the complete protocol.

21.5. What should accompany a claim of improved logical fidelity after postselection?

Show solution / guidance

The acceptance fraction, attempted and accepted shot counts, matched baseline, circuit depth, noise conditions, uncertainty, and any discarded event criteria.

IN THIS CHAPTER